Context This post is the technical background companion to Who Foots the Bill for the 2027 Semiconductor Consensus?, CXMT IPO and Memory Price Risk, and Why the AI Supercycle Keeps Extending. Those posts covered demand, pricing, and valuation. This one examines what the three AI memory supply-side technologies actually are, how proven each one is, and how they relate to each other. Related hubs: AI HBM Hub and Exclusive Analysis Hub.
TL;DR
- HBM, HBF, and HBC are not the same category of technology. HBM and HBF are memory components; HBC is the name of Qualcomm’s accelerator architecture. Lining all three up and comparing raw TB/s numbers in isolation will produce a misreading.
- Each targets a different constraint. HBM attacks the bandwidth wall, HBF attacks the capacity wall, and HBC targets inference cost and power.
- Maturity gaps are wide. HBM is in full production (5/5 stars); HBF is at simulation stage (2/5, first samples targeted for H2 2026); HBC is a blueprint (1/5, samples targeted for 2027).
- The three are complements, not substitutes. Data “temperature” determines placement: hot data (KV cache) belongs in HBM, cold data (static model weights) belongs in HBF, and low-cost inference is where HBC aims.
- No technology currently threatens HBM’s position as working memory for AI accelerators. Meaningful revenue contribution from HBF or HBC is unlikely before 2027-2028 at the earliest. [Inference]
1. The Real Bottleneck in AI Is Memory, Not Compute
GPU compute throughput has grown roughly 80x over the past decade, while memory bandwidth has grown only about 17x. [Fact: NVIDIA generation-by-generation spec comparison] That gap is the genuine bottleneck in today’s AI accelerators. Expensive AI chips spend a growing share of their time idle, waiting for data to arrive – and the speed at which an LLM generates a single token is almost entirely a function of how fast memory can ferry data to the processor.
That bottleneck breaks into two distinct walls.
The bandwidth wall: memory cannot deliver data fast enough. The decode phase of LLM inference must read the full set of model weights from memory for every token generated, which makes it permanently memory-bandwidth-bound.
The capacity wall: memory cannot hold enough data at once. The KV cache alone for a 128,000-token context window runs to roughly 343 GB – already exceeding the 192 GB of HBM capacity on the latest NVIDIA B200. [Fact: derived from public specifications]
HBM, HBF, and HBC each attack these two walls in a different way. And one of the three is not a memory component at all – it is a single company’s accelerator architecture. Missing that distinction collapses the entire comparison.
2. HBM: The Only Proven Technology, Solving the Bandwidth Wall
The Core Concept
The logic behind High Bandwidth Memory is elegant. Stack 8 to 16 DRAM dies vertically, place the stack directly beside the GPU on the same interposer, and connect them through thousands of fine electrodes called through-silicon vias (TSVs). The result is a data path 1,024 to 2,048 bits wide. Speed comes not from any individual pin running faster but from an extraordinarily wide channel – the same reason a 2,048-lane highway moves more total traffic than a narrow one-lane expressway, even if each lane is not the fastest.
Performance and Proven Maturity
A single HBM3E stack delivers roughly 1.2 TB/s of bandwidth; HBM4 targets approximately 2 TB/s. [Fact: JEDEC specifications] Both are 20 to 30 times the bandwidth of DDR5. Virtually every high-performance AI accelerator in production today – NVIDIA H100, H200, B200, AMD MI300 – ships with HBM.
Maturity rating: 5/5. HBM is the only one of the three technologies in full-volume production. Years of large-scale manufacturing have validated yield and reliability at scale. SK Hynix holds roughly 57 to 62 percent of the market and remains NVIDIA’s primary supplier. [Fact: company IR disclosures and market estimates]
Roadmap and Industry Structure
The roadmap runs from HBM4 (volume production 2026, introducing a logic-based base die) to HBM4E (custom configurations) to HBM5 (targeting 4 TB/s, 2029). Starting with HBM4, SK Hynix manufactures the base die on TSMC’s 12nm process, making HBM development a joint design effort between a memory company and a foundry. [Fact: company announcements] [Inference: the 4 TB/s target for HBM5 is a roadmap objective, not yet independently verified]
The supply side is a three-player oligopoly of SK Hynix, Samsung Electronics, and Micron, with TSMC anchoring the base die and interposer layer. The AI memory ecosystem is effectively a co-production across these five companies. [Inference: market size estimated at roughly $35 billion in 2025, growing to $45-58 billion in 2026, with significant variance across sources]
3. HBF: Targeting the Capacity Wall, Still at the Promise Stage
The Core Concept
The idea behind High Bandwidth Flash is clever: borrow HBM’s stacking geometry and interface approach, but swap the expensive DRAM inside for cheaper NAND flash. NAND can pack multiple bits per cell, delivering far greater capacity at a much lower cost per gigabyte. In August 2025, SanDisk and SK Hynix announced a joint standardization effort. SanDisk described the technology as designed to “augment, not replace, HBM.” [Fact: SanDisk/SK Hynix joint announcement]
SanDisk claims a single HBF stack can hold roughly 512 GB (8 to 16 times more than a comparable HBM stack) while delivering approximately 1.6 TB/s of bandwidth. [Fact: SanDisk fact sheet]
Maturity: An Honest Assessment
That is where the analysis needs to pause.
Maturity rating: 2/5. HBF has not entered mass production. There is no independent benchmark of a physical chip. The 512 GB and 1.6 TB/s figures are derived from SanDisk’s internal simulations; the fact sheet’s footnotes explicitly state “internal testing and simulations under specific model assumptions.” [Fact: SanDisk fact sheet footnotes] First silicon samples are targeted for H2 2026, with inference-device adoption expected no earlier than 2027. The manufacturing challenge is also non-trivial: stacking 238-layer NAND 16 dies high implies more than 5,000 total layers of accumulated process complexity.
NAND’s Weaknesses Define Its Role
Two physical constraints govern what HBF can and cannot do.
First, latency: NAND reads more slowly than DRAM. HBF’s read latency runs roughly 100 times longer than HBM’s – approximately 10 microseconds for HBF versus tens of nanoseconds for HBM. [Fact: inherent media characteristics]
Second, write endurance: NAND cells tolerate a finite number of write cycles, making the technology ill-suited to data that changes continuously.
These two constraints fix HBF’s role: a high-capacity store for model weights – data that is read repeatedly but almost never written after training completes. Within that role, both weaknesses become nearly irrelevant.
The Decisive Variable: NVIDIA’s Adoption Decision
NVIDIA has shown limited public interest in HBF. Signals from the company suggest it favors GPU-attached high-speed SSDs (eSSD) as the solution to the capacity problem. Among large hyperscalers, Google has shown the most interest in HBF. [Inference: based on industry observation and public reporting] Whether NVIDIA ultimately adopts HBF is the single biggest unknown determining whether the technology becomes a mainstream platform or a niche solution.
The industry structure is currently SanDisk-led with SK Hynix as the primary collaborator; Samsung has signaled participation. Kioxia has taken a different path, investing instead in eSSD. Sides have not yet hardened.
4. HBC: Not a Memory Standard – Qualcomm’s Accelerator Architecture
Getting the Terminology Right First
“HBC” is an acronym with a trap inside it. Placed alongside HBM and HBF, it looks like a third memory technology. It is not. HBC is the name Qualcomm gave to its own AI accelerator architecture – “High Bandwidth Compute” – announced at its investor day in June 2026. It is a single company’s brand, not an industry-agreed standard. [Fact: Qualcomm official announcement]
The “HBC” abbreviation also collides with AMD’s “High Bandwidth Cache Controller” (HBCC) and is easily confused with HBF. These are entirely unrelated concepts.
What this means for analysis: a “HBM vs HBF vs HBC” comparison is strictly two memory components versus one system architecture. Ignoring that asymmetry leads to conclusions like “HBC delivers 18x more bandwidth than HBM” – a comparison that mixes entirely different units and system-level reference points.
Technology and Approach
The memory medium inside HBC is not HBM – it is LPDDR, the low-power DRAM used in smartphones. Qualcomm’s approach is to stack this inexpensive LPDDR directly on top of a compute logic die in 3D, collapsing the distance between memory and processing to near zero. The goal is to run inference cheaply and efficiently without the cost of a silicon interposer or expensive HBM.
Qualcomm claims 6x bandwidth per watt compared to HBM, and 200x capacity per watt compared to SRAM. [Fact: Qualcomm announcement] Both figures are Qualcomm’s own claims, normalized at the card or rack level. They are not directly comparable to per-stack HBM specs; reading them alongside HBM figures without adjusting for the reference basis will produce misleading conclusions.
Maturity and Ground Truth
Maturity rating: 1/5. The Qualcomm AI250 accelerator that embeds HBC does not yet exist as silicon. Sampling is targeted for mid-2027. Every performance figure released is a design target. [Fact: Qualcomm announcement] If HBF is at the simulation stage, HBC is at the blueprint stage. Reports have circulated that Microsoft and Meta have placed orders for Qualcomm AI accelerators, but those reports remain unconfirmed. [Inference: based on secondary press coverage, not independently verified]
The correct frame for reading HBC is not “a competing memory standard to HBM” but rather “one company’s system-level strategy to run inference cheaply without using HBM." If it succeeds, it could capture a portion of the low-cost inference segment that currently uses HBM-based accelerators – but it does not present a scenario in which HBM as a category is displaced. The supply side is also effectively Qualcomm alone.
5. Complements, Not Substitutes: Data Temperature Determines Placement
Headlines declaring “HBF will kill HBM” or “HBC will replace HBM” surface regularly. The analytical conclusion from working through the technology is that these claims are overstated. The three technologies are fundamentally complementary.
That conclusion does not rest on abstract market logic. It follows from the physical nature of the data itself.
LLM inference puts two categories of data into memory.
Model weights (cold data): fixed after training, read continuously during inference, almost never written. A large, slow, inexpensive memory tier (HBF) is an entirely adequate home for this data. NAND’s write-endurance constraint is nearly irrelevant when the data is read-only.
KV cache (hot data): updated continuously as a conversation or generation sequence progresses. It must live in the fastest available memory (HBM). Moving it to a slower tier slows the entire inference pipeline.
With a roughly 100x latency gap between them, HBM and HBF cannot occupy the same working-memory role. HBF does not displace HBM; it receives what HBM cannot hold, functioning as a lower tier in the hierarchy. HBC operates on an entirely different track, targeting low-cost inference economics rather than serving as a memory upgrade.
The most likely direction for future AI accelerator platforms is not a binary choice between HBM and HBF but a three-tier stack of HBM plus HBF plus high-speed SSD, with each layer serving data at the appropriate temperature. [Inference: technology roadmap analysis]
Partial competition does exist. Whether capacity extensions are solved through HBF or through eSSD is still an open contest. In the low-cost inference segment, HBC-based and HBM-based accelerators will overlap to some degree. And if HBF or HBC succeeds in making “large capacity at low cost” a viable option, some customers will have a reason to buy less HBM at the margin. But all of these competitive dynamics play out in 2027 and beyond.
6. Milestones to Watch
All three technologies are at different points on the journey from announced to proven.
HBM is the ongoing story. The next inflection points are HBM4 production yield, the rollout of custom HBM configurations tailored to specific hyperscaler needs, and the transition to hybrid bonding. SK Hynix, Samsung, Micron, and TSMC will capture the large majority of AI memory value creation in the near term. [Inference: market share projections]
For HBF, two milestones dominate. First: the arrival of first physical samples and independent benchmarks in H2 2026. Every number published to date is a simulation result; the moment real silicon can be tested independently is when the technology’s claims can be evaluated against reality. Second: whether NVIDIA elects to adopt HBF. An NVIDIA design win would rapidly crystallize the HBF ecosystem; the absence of one leaves the technology in a limited-customer camp.
For HBC, the first gate is Qualcomm’s AI250 reaching silicon in 2027 and passing independent verification. Confirmed orders from Microsoft and Meta would signal whether an HBC-compatible ecosystem is forming or whether Qualcomm remains the sole actor.
Hype Check
Several claims circulate in coverage of this space that warrant caution.
“HBF and HBC will replace HBM”: The latency gap and role differentiation make a complementary structure far more plausible than a replacement narrative. The displacement story is overstated.
“16x capacity, 4 TB VRAM, 6x power efficiency”: The majority of these figures are internal simulations or design targets, not independently measured results.
“HBM faces serious competitive threat in 2026”: Meaningful revenue contribution from HBF or HBC is unlikely before 2027 to 2028 at the earliest.
“HBC is a next-generation memory technology”: This is a category error. HBC is Qualcomm’s accelerator architecture, not a memory standard.
The correct starting point for analysis is separating marketing headlines from independently verified facts – and recognizing where the evidence stops and the promise begins.
This post is a technology analysis based on publicly available primary, secondary, and tertiary sources and company announcements. It is not a recommendation to buy or sell any security or product. Performance figures cited for HBF and HBC are predominantly company claims, simulation results, or design targets that have not yet been independently verified. This field is evolving rapidly; readers are encouraged to cross-check the latest primary sources before drawing investment conclusions.